This application claims the benefit of a Japanese Patent Application No. 2001-350323 filed Nov. 15, 2001 in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a ferroelectric film.
Semiconductor devices such as so-called Dynamic Random Access Memory (DRAM)s or Static Random Access Memory (SRAM)s are used extensively as a high-speed main memory device in various information processing apparatuses including computers. These semiconductor devices, however, have volatile memories and the information stored therein is lost when the power is turned OFF. Conventionally, nonvolatile magnetic disk units have been used as large-capacity secondary storage devices for storing programs and data.
However, magnetic disk units have disadvantages in that they are bulky and fragile, have large power consumption, and furthermore in that they have low access speed upon reading and writing information. Recently, Electrically Erasable Programmable Read Only Memory (EEPROM)s or flash-memory devices are frequently used for storing information in a floating-gate electrode in the form of electrical charges. Particularly, flash-memory devices tend to have a high integration density because they have cell construction similar to that of DRAM, and are expected to become the large-capacity storage device comparable to a magnetic disk unit.
In EEPROM and flash-memory devices, writing of information is achieved by injecting hot electrons through a tunneling insulation film into the floating gate electrode. Thus, a flash-memory device has drawbacks in that it inevitably takes a substantial time for writing and tunneling insulation film deteriorates after writing and erasing operations are repeated a number of times. When tunneling insulation film is deteriorated, operations of writing and erasing become unstable.
In view of the above, a ferroelectric memory device(designated hereinafter as FeRAM) for storing information in a ferroelectric film in the form of a spontaneous polarization is proposed. In such FeRAM, an individual memory cell transistor, consisting of a single MOSFET as in the case of DRAM, comprises a structure in which dielectric film in the memory cell capacitor is replaced by ferroelectric material such as PZT (Pb(Zr, Ti)O3) or PLZT(Pb(Zr,Ti,La)O3), and furthermore, SBT(SrBi2Ta2O3), or SBTN(SrBi2(Ta,Nb)2O3); and it becomes possible to integrate at high integration density. Moreover, FeRAM has an advantageous feature that because it controls the spontaneous polarization of the ferroelectric capacitor by applying an electric field, writing operation is achieved with a high speed, faster by a factor of 1000 or more than the EEPROM or flash-memory devices which carries out writing by injecting hot electrons, and the power consumption is reduced to about 1/10 compared to the EEPROM or flash-memory device. Furthermore, lifespan is longer because there is no need to use the tunneling oxide film; the FeRAM device can be erased 10 million times or more.
2. Description of the Related Art
FIG. 1 shows a structure of FeRAM 10 disclosed in a Japanese Laid-Open Patent Application No. 2000-156470.
Referring to FIG. 1, FeRAM 10 is formed on a Si substrate 11 in correspondence to an active region defined by a device isolating insulation film 12. FeRAM 10 includes gate electrode 13 formed on the Si substrate 11 via gate insulation film not shown in the Figure, and diffusion regions 11A and 11B formed on either side of the gate electrode 13 in the Si substrate 11.
Interlayer insulation film 14 is formed on the Si substrate 11 so as to cover the gate electrode 13. A ferroelectric capacitor in which a lower electrode 15, a ferroelectric film 16, and an upper electrode 17 are consecutively layered is formed on the interlayer insulation film.
The ferroelectric capacitor is covered with a separate interlayer insulation film 18 formed on the interlayer insulation film 14. Contact holes 18A, 18B that pass through the interlayer insulation film 14 and expose diffusion regions 11A and 11B, respectively, are formed in the interlayer insulation film 18. Additionally, contact hole 18C exposing the lower electrode 15, and contact hole 18D exposing the upper electrode 17 are formed in the interlayer insulation film 18.
In FeRAM 10 of FIG. 1, contact holes 18A through 18D are filled with contact plugs 19A through 19D, respectively, with a consecutively layered structure of TiN film, A—Cu film, TiN film and WSi film. Furthermore, interconnecting patterns contacting the contact plugs are formed on the interlayer insulation film 18.
Recently in particular, conductive oxide such as IrOx or SrRuOx is frequently used as the upper electrode of the ferroelectric capacitor used in FeRAM. Such conductive oxide is similar to ferroelectric film consisting of oxide in terms of chemical and crystallographic properties, and is convenient in optimizing the electrical property of ferroelectric film.
In the FeRAM 10 of FIG. 1, contact plugs 19A through 19D are formed by a sputtering method. However, in the sputtering method, if a semiconductor device is miniaturized, step coverage in contact holes 18A through 18D easily form defects and a problem of yield and reliability arises.
In a general semiconductor device, such contact plugs are frequently formed by depositing a W layer by means of a Chemical Vapor Deposition (CVD) method, and then removing the W layer on the insulation film by means of a Chemical Mechanical Planarization (CMP) method. It is possible to securely fill the contact holes with W plugs by the CVD method even in contact holes where the aspect ratio is large.
However, in semiconductors with ferroelectric film such as FeRAM, attempts to deposit a W layer by means of the CVD method develop a problem where H2 contained in the atmosphere during deposition acts on the ferroelectric film and reduces the ferroelectric film. When ferroelectric film is reduced, the electrical property with a characteristic of desired hysteresis is lost.
In an attempt to avoid this problem, steps of forming W plugs for diffusion regions, and then forming contact plugs for the ferroelectric capacitor can be considered.
In FeRAM 10 of FIG. 1, it may be considered to, for example, first form contact holes 18A and 18B, and then after filling the contact holes 18A, 18B with W plugs 19A and 19B, respectively, to form contact holes 18C, 18D. According to such staging, in the formation of W plugs 19A and 19B, a ferroelectric film 16 is sealed by interlayer insulation film 18 and the problem of ferroelectric film reduction can be avoided.
In such a method, however, it is necessary to form contact holes 18C and 18D in the ferroelectric capacitor by a dry etching method. This dry etching method involves, especially if upper electrode 17 is formed by conductive oxide film, the upper electrode 17 and ferroelectric film 16 underlying the upper electrode will be partially reduced, and a problem of oxygen defect arises.
For this reason, in the case where contact holes 18C and 18D are formed afterward, heat treatment in the oxidizing atmosphere to compensate for oxygen defect is necessary. However, when conducting heat treatment in the oxidizing atmosphere, previously formed W plugs 19A and 19B oxidize, and a problem concerning increase in contact resistance arises.